MSc Proposal 2024-25
Name
INVM
Title
Dissertation: Overcoming Memory Limitations in Programmable Switches with In-Network Virtual Memory
Advisor(s)
Objectives
Recent advancements in programmable data planes and the popularization of the P4 programming language have led to an explosiong of potential network applications for various purposes. These include ML-based traffic analysis, in-band network telemetry, congestion control, load balancing, caching, and security and privacy.
However, developing P4 applications for existing programmable switches poses significant challenges due to the limited available memory on the hardware. This memory shortage can severely restrict the functionality of applications that network operators can run on the data plane, thus stifling innovation. P4 developers may attempt to overcome these limitations through code-level optimizations; however, these tend to be difficult to implement and application- and hardware-dependent, thereby narrowing the applicability of these techniques. Moreover, new emerging applications can certainly benefit from higher memory capacity for storing certain types of information on switches, e.g., from stateless serverless functions to collaborative AR/VR applications with very low latency requirements.
The goal of this thesis project is to explore the feasibility of an alternative solution to overcome data plane memory limitations without requiring P4 developers to delve into the low-level specifics of the hardware or design tailor-made optimizations. Specifically, we propose developing an in-network virtual memory (INVM) mechanism that can transparently leverage the control plane as a medium for creating a swapping space for data plane memory. As with classical virtual memory for CPUs, this approach will create the illusion of a virtual address space for P4 applications on the switch that is significantly larger than the physical memory actually present.
To materialize INVM, we will investigate several open questions. First, given the significant latency between the control plane and the data plane, we propose speeding up this access by creating an intermediary memory hierarchy layer, acting as a cache. This layer would consist of an elastic buffer stored in the form of dedicated packets recirculating through the switch. We expect this buffer to help reduce memory access latencies and lower the cost of swapping operations. Second, since the data plane lacks a hardware-assisted memory management unit, we need to explore a software-based approach to offering a virtual memory API, likely through a memory management library. We will study which programming abstractions, such as key-value stores, are most suitable for facilitating access to virtual memory. Lastly, in addition to extensively measuring the potential benefits and limitations of our approach in terms of performance and resource utilization on real Tofino switches, we will collect representative P4 applications from different domains to benchmark our system.
Requirements
We seek a highly motivated student with deep interest in networked systems and P4.
Location
IST-Alameda (INESC-ID) or IST-Tagus
Observations
This work will be performed in collaboration with Dr. Eduard Fabregas, a Research Scientist at Telefonica Research. This topic is already reserved for a student.